Transistors are commonly utilized in integrated circuitry. The transistors will comprise a gate through which a pair of source/drain regions can be electrically coupled with one another. The transistor gate can comprise conductively-doped semiconductor material such as, for example, n-type doped silicon or p-type doped silicon.
It is frequently desired to optimize transistor performance relative to particular circuitry incorporating the transistor. Such optimization can include utilization of n-type doped silicon within the transistor gate in some applications, and in other applications such optimization can include utilization of p-type doped silicon within the transistor gate.
Integrated circuitry is typically formed over a semiconductor substrate, and it is not uncommon for transistor gates containing n-type doped silicon to be over one region of the substrate while transistor gates containing p-type doped silicon are over another region of the substrate. For instance, transistor gates containing n-type doped silicon can be desired for utilization across a memory array region of a substrate, and transistor gates containing p-type doped silicon can be desired for utilization in logic circuitry peripheral to the memory array region.
A continuing goal during fabrication of semiconductor constructions is to reduce process steps to save time and reduce costs. It would be desirable to develop processes by which transistor gates containing p-type doped silicon are simultaneously patterned with transistor gates containing n-type doped silicon. Some efforts have been made to accomplish this, but difficulties are encountered in that commonly-utilized silicon etches are fairly highly selective for one of n-type doped silicon and p-type doped silicon relative to the other. Thus, the etches tend to proceed much more rapidly through one of n-type doped silicon and p-type doped silicon relative to the other, which can result in significant over-etching in applications in which it is attempted to simultaneously pattern transistor gates containing p-type doped silicon with transistor gates containing n-type doped silicon.
As will become clear in the discussion of the present invention presented below, some aspects the invention address the above-discussed problems of simultaneously patterning transistor gates containing p-type doped silicon with transistor gates containing n-type doped silicon. However, it should be understood that even though the invention was motivated at least in part by a desire to address such problems, the invention has applications beyond this.